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7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 1 rev1 march 2012 idt f1950 datasheet g eneral d escription this document describes the specification for the idtf1950 digital step attenuator. the f1950 is par t of a family of glitchfree tm dsas optimized for the demanding requirements of communications infrastructure. the se devices are offered in a compact 4x4 qfn package wi th 50 impedances for ease of integration into the radio system. c ompetitive a dvantage digital step attenuators are used in receivers and transmitters to provide gain control. the idtf1950 is a 7bit step attenuator optimized for these demanding applications. the silicon design has very low inse rtion loss and low distortion (+65 dbm ip3 i .) the device has pinpoint accuracy and settles to final attenuation value within 400 nsec. most importantly, the f1950 inclu des idts g g l l i i t t c c h h - - f f r r e e e e t t m m technology which results in less than 0.6 db of overshoot ringing during msb transit ions. this is in stark contrast to competing dsas that glitch as much as 10 db during msb transitions (see p.10) l l o o w w e e s s t t i i n n s s e e r r t t i i o o n n l l o o s s s s f f o o r r b b e e s s t t s s n n r r g g l l i i t t c c h h f f r r e e e e t t m m w w h h e e n n t t r r a a n n s s i i t t i i o o n n i i n n g g C C w w o o n n t t d d a a m m a a g g e e p p a a o o r r a a d d c c e e x x t t r r e e m m e e l l y y a a c c c c u u r r a a t t e e w w i i t t h h l l o o w w d d i i s s t t o o r r t t i i o o n n a pplications ? base station 2g, 3g, 4g, tdd radiocards ? repeaters and e911 systems ? digital predistortion ? point to point infrastructure ? public safety infrastructure ? wimax receivers and transmitters ? military systems, jtrs radios ? rfid handheld and portable readers ? cable infrastructure p art # m atrix part# freq range resolution / range control il pinout f f 1 1 9 9 5 5 0 0 1 1 5 5 0 0 4 4 0 0 0 0 0 0 0 0 . . 2 2 5 5 / / 3 3 1 1 . . 7 7 5 5 p p a a r r a a l l l l e e l l & & s s e e r r i i a a l l 1 1 . . 3 3 p p e e f1951 100 4000 0.50 / 31.5 serial only 1.2 hitt f1952 100 C 4000 0.50 / 15.5 serial only 0.9 hitt f eatures ? glitchfree tm , < 0.6 db transient overshoot ? spurious free design ? 3v to 5v supply ? attenuation error < 0.3 db @ 2 ghz ? low insertion loss < 1.3 db @ 2 ghz ? excellent linearity +65 dbm ip3 i ? fast settling time, < 400 nsec ? class 2 jedec esd (> 2kv hbm) ? serial & parallel interface 31.75 db range ? 4x4 mm thin qfn 24 pin package d evice b lock d iagram o rdering i nformation rf 1 bias v dd v mode dec d[6:0] 7 clk spi le data rf 2 idt f1950nbgi8 0.8 mm height package green industrial temp range tape & reel omit idt prefix rf product line glitch-free tm glitch-free tm
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 2 rev1 march 2012 idt f1950 datasheet a bsolute m aximum r atings v dd to gnd 0.3v to +5.25v d[6:0], data, clk,le, v mode 0.3v to 3.6v rf input power (rf1, rf2) calibration and testing + 29 dbm rf input power (rf1, rf2) continuous rf operation + 23 dbm ja (junction C ambient) +50c/w jc (junction C case) the case is defined as the exposed paddle +3c/w operating temperature range (case temperature) t c = 40c to +100c maximum junction temperature 140c storage temperature range 65c to +150c lead temperature (soldering, 10s) . +260c
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 3 rev1 march 2012 idt f1950 datasheet idtf1950 s pecification (31.75 db range) specifications apply at v dd = +3.3v , f rf = 2000mhz , and t c = +25c, evkit losses are deembedded (see p. 17) f or spec purposes parameter comment sym. min typ ical max units logic input high clk, le, data, d[6:0], v mode v ih 2.3 3.6 v logic input low clk, le, data, d[6:0], v mode v il 0.7 v logic current v mode i ih, i il -5 +5 a supply voltage(s) main supply v dd 3.0 to 5.25 v supply current total i dd 0.25 0.5 1 ma temperature range operating range (case) t c 40 to +100 degc frequency range operating range f rf 150 to 4000 mhz rf1, rf2 return loss db(s11), db(s22) s 11 , s 22 22 db minimum attenuation d[6:0] = [0000000] a m in or il 1.3 1.9 db maximum attenuation d[6:0] = [1111111] a max 32.6 33.0 db minimum gain step least significant bit lsb 0.25 db phase delta phase change a min vs. a max ? 34 deg differential nonlinearity max error between adjacent steps dnl 0.10 db integral nonlinearity max error vs. line (a min ref) to 13.75 db attn inl 1 0.02 0.30 db integral nonlinearity max error vs. line (a min ref) to 31.75 db attn inl 2 0.27 0.45 db input ip3 d[6:0] = [0000000] = a min d[6:0] = [0111111] = a 15.75 d[6:0] = [1111111] = a max p in = +10 dbm per tone 50 mhz tone separation ip3i 1 ip3i 2 ip3i 3 +60 2 +59 +57 +63 +61 +61 dbm 0.1 db compression please note abs max input power on page 2 d[6:0] = [0001010] = a 2.5 baseline p in = 20 dbm p 0.1 27.5 dbm settling time start le rising edge > v ih end +/0.10 db pout settling 15.75 C 16.00 transition t lsb 400 nsec serial clock speed spi 3 wire bus f cl k 20 50 mhz parallel to serial setup spi 3 wire bus a 100 ns serial data hold time spi 3 wire bus b 10 ns le delay from final serial clock rising edge spi 3 wire bus c 10 ns s pecification n otes : 1 C items in min/max columns in bold italics are guaranteed by test 2 C all other items in min/max columns are guarante ed by design characterization
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 4 rev1 march 2012 idt f1950 datasheet s erial c ontrol m ode serial mode is selected by floating v mode (pin3) or pulling it to a voltage > v ih . in serial mode data is clocked in lsb first. note the timing diagram below. note C the idtf1950 includes a clk inhibit feature designe d to minimize sensitivity to clk bus noise when the device is not being programmed. when latch enable is high (> v ih ), the clk input is disabled and data will not be c locked into the shift register. it is recommended that le be pulled high (> v ih ) when the device is not being programmed. s erial r egister t iming d iagram : (note the timing spec intervals in blue ) s erial m ode d efault c ondition : when the device is powered up it will default to th e maximum attenuation setting as described below: note that for the f1950 in all cases (high or 1) = attenuation stepped in . (0 or low) = attenuation stepped out . s erial m ode t iming t able : interval symbol description min spec max spec units a parallel to serial setup time 100 nsec b serial data hold time 10 nsec c le delay from final serial clock rising edge 10 ns ec data word 8 bits d0 d1 d5 d2 d4 d3 0.5 db clk data data word latched into active register lsb d7 0.25 db 1 2 3 4 5 6 7 8 9 1 db 2 db 4 db 8 db 16 db msb x d6 rsv le v mode spec interval a b c time default register settings 1 0 1 1 1 1 1 1 d7 d6 d2 d5 d3 d4 rsv d0 msb d1 lsb
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 5 rev1 march 2012 idt f1950 datasheet p arallel c ontrol m ode the user has the option of running in one of two pa rallel modes: direct parallel mode or latched parallel mode. d irect p arallel m ode : direct parallel mode is selected when v mode (pin 3) is < v il and le (pin 16) is > v ih . in this mode the device will immediately react to any voltage change s to the parallel control pins [pins 19, 20, 21, 22 , 23, 24, 1]. use direct parallel mode for the fastest s ettling time. l atched p arallel m ode : latched parallel mode is selected when v mode (pin 3) is < v il and le (pin 16) is toggled from < v il to > v ih to utilize latched parallel mode: set le < v il adjust pins [19, 20, 21, 22, 23, 24, 1] to the des ired attenuation setting. (note the device will not react to these pins while le < v il .) pull le > v ih . the device will then transition to the attenuatio n settings reflected by these pins. latched parallel mode implies a default state for w hen the device is powered up with v mode < v il and le < v il . in this case the default setting is maximum attenua tion. l atched p arallel m ode t iming d iagram : (note the timing spec intervals in blue ) l atched p arallel m ode t iming t able : interval symbol description min spec max spec units a serial to parallel mode setup time 100 nsec b parallel data hold time 10 nsec c le minimum pulse width 10 nsec d parallel data setup time 10 nsec d[6:0] data word latched into active register le v mode spec intervals a d c b
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 6 rev1 march 2012 idt f1950 datasheet t ypical o perating p arametric c urves (evkit loss de-embedded unless otherwise noted) insertion loss vs. frequency [a min ] s 11 vs. frequency [t case = +25c, 0.75 db steps] s 11 vs. attenuation state attenuation vs. freq [t case = +25c, 0.75 db steps] s 22 vs. frequency [t case = +25c, 0.75 db steps] s 22 vs. attenuation state 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v rf frequency (mhz) insertion loss (db) 40 35 30 25 20 15 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 rf frequency (mhz) rf1 return loss (db) 40 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 40 degc 3.3 v 900 mhz 40 degc 3.3 v 2000 mhz 25 degc 3.3 v 900 mhz 25 degc 3.3 v 2000 mhz 100 degc 3.3 v 900 mhz 100 degc 3.3 v 2000 mhz rf1 return loss (db) attn setting (db) 35 30 25 20 15 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 rf frequency (mhz) dsa loss (db) rf frequency (mhz) dsa loss (db) rf frequency (mhz) dsa loss (db) 40 35 30 25 20 15 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 rf frequency (mhz) rf2 return loss (db) 40 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 40 degc 3.3 v 900 mhz 40 degc 3.3 v 2000 mhz 25 degc 3.3 v 900 mhz 25 degc 3.3 v 2000 mhz 100 degc 3.3 v 900 mhz 100 degc 3.3 v 2000 mhz rf2 return loss (db) attn setting (db)
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 7 rev1 march 2012 idt f1950 datasheet toc s continued (-2-) phase vs. frequency supply current i dd input ip3 [f rf = 1900 mhz] phase vs. attenuation setting input ip3 [f rf = 900 mhz] compression [f rf = 2000 mhz, attn = 2.5 db] 110 100 90 80 70 60 50 40 30 20 10 0 10 200 600 1000 1400 1800 2200 2600 3000 3400 3800 40 degc 31.75 db 40 degc 0.00 db 25 degc 31.75 db 25 degc 0.00 db 100 degc 31.75 db 100 degc 0.00 db rf frequency (mhz) s21 phase (degrees) 0.0 0.2 0.4 0.6 0.8 1.0 0 5 10 15 20 25 30 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) i dd (ma) 10 20 30 40 50 60 70 80 90 0 4 8 12 16 20 24 28 40 degc 5.00 v 40 degc 2.97 v 25 degc 5.00 v 25 degc 2.97 v 100 degc 5.00 v 100 degc 2.97 v attenuation setting (db) input ip3 (dbm) 100 90 80 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 150 mhz 400 mhz 900 mhz 1400 mhz 1900 mhz 2400 mhz 2900 mhz 3400 mhz 3900 mhz attenuation setting (db) s21 phase (degrees) 10 20 30 40 50 60 70 80 90 0 4 8 12 16 20 24 28 40 degc 5.0 v 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 5.0 v 100 degc 3.3 v attenuation setting (db) input ip3 (dbm) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 20 21 22 23 24 25 26 27 28 29 loss compression (db) input power (dbm) 40 degc 5.0 v 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 5.0 v 100 degc 3.3 v
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 8 rev1 march 2012 idt f1950 datasheet toc s continued (-3-) dnl [150 mhz] dnl [900 mhz] dnl [2800 mhz] dnl [450 mhz] dnl [1900 mhz] worst setting dnl 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 100 600 1100 1600 2100 2600 3100 3600 4100 worst setting step error (db) rf frequency (mhz) 5v min dnl 5v max dnl 3.3v min dnl 3.3v max dnl
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 9 rev1 march 2012 idt f1950 datasheet toc s continued (-4-) inl [150 mhz] inl [900 mhz] inl [2800 mhz] inl [450 mhz] inl [1900 mhz] worst setting inl 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) absolute error (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) absolute error (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) absolute error (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) absolute error (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 3.3 v attenuation setting (db) absolute error (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0.50 100 600 1100 1600 2100 2600 3100 3600 4100 worst setting absolute error (db) rf frequency (mhz) 5v min dnl 5v max dnl 3.3v min dnl 3.3v max dnl
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 10 rev1 march 2012 idt f1950 datasheet toc s continued (-5-) [f rf = 900 mhz] transient [ 15.75 to 16.00 (msb+) 3.3v f1950 ] the graphs above show the transient overshoot and settling time performance for both the msb+ and msb cases for the f1950. the device settles very quickly (~400) nsec with benign (~0.5) db overshoot . transient [ 15.75 to 16.00 (msb+) standard dsa ] transient [ 16.00 to 15.75 (msb-) 5.0v f1950 ] the graphs below show the transient overshoot and settling time performance for a popular competing dsa. n n o o t t e e t t h h e e o o v v e e r r s s h h o o o o t t / / u u n n d d e e r r s s h h o o o o t t e e x x c c u u r r s s i i o o n n o o f f a a l l m m o o s s t t 1 1 0 0 d d b b and the very long settling time. for the msb case, the settling time is off the scale, ~ 3 usec. transient [ 16.00 to 15.75 (msb-) standard dsa ] 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 11.88 10.88 9.88 8.88 7.88 6.88 5.88 4.88 3.88 2.88 1.88 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) glitch < 0.6 db pwr (dbm) trigger settling time = 400 nsec (+/- 0.1 db) 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 15.20 14.20 13.20 12.20 11.20 10.20 9.20 8.20 7.20 6.20 5.20 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) pwr (dbm) trigger settling time = 600nsec (+/- 0.1 db) 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 12.13 11.13 10.13 9.13 8.13 7.13 6.13 5.13 4.13 3.13 2.13 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) glitch < 0.60 db pwr (dbm) trigger settling time = 350 nsec (+/- 0.1 db) 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 13.57 12.57 11.57 10.57 9.57 8.57 7.57 6.57 5.57 4.57 3.57 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) pwr (dbm) trigger settling time >> 1 usec
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 11 rev1 march 2012 idt f1950 datasheet p in d iagram (f1950) gnd v mode d1 d2 d5 d3 gnd *rf2 clk gnd *rf1 gnd le v dd d4 d0 exposed pad d6 gnd gnd gnd gnd 2 1 3 5 4 6 package drawing 4 mm x 4 mm package dimension 2.60 mm x 2.60 mm exposed pad 0.5 mm pitch 24 pins 0.75 mm height 0.25 mm pad width 0.40 mm pad length 14 13 15 17 16 18 8 7 9 11 10 12 20 19 21 23 22 24 gnd gnd data c o 0 .3 5 mm * device is rf bi-directional
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 12 rev1 march 2012 idt f1950 datasheet p ackage d rawing (4 x 4 24 pin )
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 13 rev1 march 2012 idt f1950 datasheet p in d escriptions pin # pin name pin function 1 do parallel control C 0.25 db attenuation step. pull high for 0.25 db attenuation. 2 v dd main supply. use 3.3v or 5v. current is < 1 ma. 3 v mode pull low for parallel mode. pull high or leave unc onnected for serial mode. 4 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 5 rf1 device rf input or output (bidirectional). must a c couple to this pin. 6 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 7 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 8 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 9 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 10 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 11 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 12 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 13 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 14 rf2 device rf input or output (bidirectional). must a c couple to this pin. 15 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 16 le latch enable. serial data latched into active regi ster on rising edge. 17 clk serial clock input 18 data serial data input 19 d6 parallel control C 16 db attenuation step. pull hi gh for 16 db attenuation. 20 d5 parallel control C 8 db attenuation step. pull hig h for 8 db attenuation. 21 d4 parallel control C 4 db attenuation step. pull hig h for 4 db attenuation. 22 d3 parallel control C 2 db attenuation step. pull hig h for 2 db attenuation. 23 d2 parallel control C 1 db attenuation step. pull hig h for 1 db attenuation. 24 d1 parallel control C 0.5 db attenuation step. pull h igh for 0.5 db attenuation. ep exposed paddle connect to ground with multiple vias for good therm al relief.
7 bit 0.25 db digital step attenuator glitchfree tm digital step attenuator ev kit s chematic the diagram below describes the recommended applica tions / evkit circuit: bit 0.25 db digital step attenuator 150 mhz to 4000 mhz 14 the diagram below describes the recommended applica tions / evkit circuit: 150 mhz to 4000 mhz rev1 march 2012 idt f1950 datasheet
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 15 rev1 march 2012 idt f1950 datasheet evk it o peration (email: rfsupport@idt.com to request an evkit, serial control hw/sw , or trl cal board) the picture and graphic below describe how to opera te the evkit rf1 dc power serial control port unused rf2 data clock latch enable set to 0 to use dip switch 0.25 db lsb 16 db msb
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 16 rev1 march 2012 idt f1950 datasheet evk it bom t op m arkings f1950 bom rev 02 pcb rev 01 item # value size desc mfr. part # mfr. part reference qty 1 1000pf 0402 cap cer 1000pf 50v c0g 0402 grm1555c1h102ja01d murata c13,14 2 2 10nf 0402 cap cer 10000pf 16v 10% x7r 0402 GRM155R71C103KA01D murata c2,12 2 3 0.1uf 0402 cap cer 0.1uf 16v 10% x7r 0402 grm155r71c104ka88d mur ata c1,11 2 4 header 2 pin th 2 conn header vert sgl 2pos gold 9611026404ar 3m j5,7 2 5 header 4 pin th 4 conn header vert sgl 4pos gold 9611046404ar 3m j8 1 6 header 8 pin th 8 conn header vert sgl 8pos gold 9611086404ar 3m j6 1 7 sma_end_launch .062 sma_end_launch (small) 1420711821 emerson johnson j2,3,4 3 8 0 0402 res 0.0 ohm 1/10w 0402 smd erj2ge0r00x panasonic r18,12 9 9 3k 0402 res 3.00k ohm 1/10w 1% 0402 smd erj2rkf3001x panasonic r911 3 10 100k 0402 res 100kohm 1/10w 0402 smd erj2gej104x panasonic r13,14 2 11 dipswitch th 10 8 position dip switch kat1108e eswitch u1 1 12 digital step attenuator f1950z f1950z idt u2 1 13 pcb pcb rev 01 f195xs evkit rev 01 1 total 30 idtf19 50nbgi z206aga lot code part number
7bit 0.25 db digital step attenuator 150 mhz to 4000 mhz glitchfree tm digital step attenuator 17 rev1 march 2012 idt f1950 datasheet evk it t hrough -r eflect -l ine (trl) c alibration the throughreflectline (trl) method [1] is used to deembed the evaluation board losses from the s parameter measurements of the f1950. this method requires the use of three standa rds: a through, a reflection, and a line. the trl m ethod has the advantage over other calibration methods in that it requires only one of these three standards to be well defined. the trl through which is used for the f1950 trl cal ibration was constructed identically to the evaluat ion board, minus the dut and its corresponding length. therefore, the through corres ponds to a precise zero length connection between t he input and output reference planes of the dut. this through satisfies the requi rement of the trl method that one of the three stan dards be precisely specified. the trl reflection standard used is constructed ide ntically to the input and output lines of the evalu ation board, with a short placed at the reference plane of the dut. in accordance with the trl methods requirements, the actual magnitude and phase were not accurately specified, but the phase was known to within 90 deg rees and the trl reflection standard has a magnitud e close to one. the trl line standard is identical to the trl throu gh, but with an additional length of 0.8 inches (2 cm). this satisfies the trl methods requirement that the trl be a different length than the trl through, that it have the same impedance a nd propagation constant as the through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. the difference in length yields a phase difference of approximately 20 degre es at 500 mhz, and a phase difference of 160 degree s at 4 ghz. for characterization of performance from 150 to 500 mhz a separate trl board with different line len gth is used. standards used for f195x trl calibration f1950 evaluation circuit engen, g.f.; hoer, c.a.; thrureflectline: an i mproved technique for calibrating the dual sixport automatic network analyzer, ieee transactions on microwave theory and techniques , volume: 27 issue:12, pp. 987 C 993, dec 1979.

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